NAME
Address Email
Phone
PROFESSIONAL OBJECTIVE:
Seeking a full time position in the field of Electronics and Computer
Engineering.
EDUCATION:
Masters of Sciences in Electrical and Computer Engineering July
2006
Bachelor of Technology in Electronics and Communication Engineering May 2003
PROJECT EXPERIENCE:
Computer Architecture: (Verilog
Simulator-Spectre; Library: AMI 0.35µ standard library; Language: VerilogHDL).
· Designed Five Stage 32 bit Pipelined CPU at 100 MHz.
Pipelined stages included Instruction fetch, Instruction decode, Execute,
Memory and Write back. Design included 32-bit ALU with worst case delay of 8
nsec, Register file implemented as two bus architecture and a Controller for
pipelined CPU. Further extended its application by adding delayed branch
prediction method for branching.
· Designed
Branch prediction logic for Scalar Processor mentioned above. Instead of
delayed branching the processor should fetch from predicted branch without
delay. To achieve this Branch prediction buffer and branch target buffer were
designed. Branch target buffer was organized as 16-line cache and Prediction
buffer as 2-bit saturating counter state machine.
· Designed
Reservation Station- Functional unit of super scalar processor. A
reservation station consisted of four buffers (four instruction could be present
simultaneously) accomplished following operations.
Allocate: The dispatch stage writes tag
values/operands into station setting the corresponding busy bits.
If operands are available valid bits are set.
Wait: The station monitors tag buses from execution state to find
matches for missing operands.
Issue: The reservation issues the instruction, which
is ready for execution-to-execution pipeline which is prioritized.
VLSI Circuit Design
(layouts):
(Design simulator: Cadence-
Spectre; Design & Schematic layout: Cadence Virtuoso layout editor;
Technology: AMI 0.6µ C5N (3M, 2P, high-res)).
· Designed an 8-Bit Digital to Pulse Width Modulated
Analog Converter connected to bi-directional I/O Pad frame, with worst case
delay 5nsec.Design includes 8-bit Loadable register, 8-bit Loadable counter,
Multi-bit Comparator and Incrementer. Register cells were designed using single
and two phase clocking. I/O pad frame available had 40 pins with 38
bi-directional signal pads,rest two being Vdd,Gnd.
· Designed
an 8-Bit Digital to Pulse Width Modulator Analog Converter to bi-directional
I/O Pad frame using Automatic Layout Design. Design includes verilog coding to
design Loadable register, Loadable counter, Multi-bit Comparator and
Incrementer.
Web Designing: (Languages:
VB.NET, ASP.NET, XML, XSL; Databases: SQL, Access)
· Designed a 3-Tier System Architecture using components
written in VB.NET. Design includes use of SQL and Access Database, validation
of data before storing the data in the database, Search facility, Customer
personalization features and Administrator features. Database tables are
created and deleted dynamically.
· The
project which includes all the above features indicated can be viewed in the
following link http://ecommerce.msis.okstate.edu/team1vb/main1.aspx.
Power Line Communication:
· Designed a hardware that supports transmission of
voice signals through power lines. Project includes designing and building of a
transmitter, receiver and a power unit using electronic elements like
transistors, OPAMPs, IC’s (555,556) and capacitors for noise cancellation.
WORK EXPERIENCE:
Research Assistant
(Remote Sensing), Oklahoma State
University January 2005- July 2006
· Worked on a project for United States Department of
Agriculture Conservation Reserve Program (CRP). This work was supported by
Oklahoma NASA EPSCoR Research Initiation Grant and Water Research Center Grant,
Oklahoma State University.
· The
work includes addressing the problems faced by USDA (CRP Compliance Monitoring
and Mapping). CRP compliance monitoring is aimed at checking whether each CRP
tract is compliant with contract stipulations. Whereas CRP Mapping is aimed at
updating accurate CRP maps required for reference and assessment activities.
· Project
includes Support Vector Machines as a classifier and bootstrapping techniques
to reduce the affect of the outliers. Programming is done in C++ and MATLAB.
Image processing is done in Adobe Photoshop.
· We
proposed a new iterative edited-bootstrapped technique which improves the
efficiency of a classifier by eliminating the outliers from the training data
set.
Teaching Assistant, Koneru Lakshmaiah College of Engineering August 2003- June
2004
· Responsibilities included teaching Digital
communication and Linear Control Systems courses, conducting exams and grade
students.
· Supervision
of students in electronic instruments laboratory and in using software that
include MATLAB, PSPICE and C++.
RELATED COURSE
WORK:
Digital Signal
Processing, Digital Electronics & logic design, Digital Computer Design
& Advance Computer Architecture, Digital VLSI Circuit Design,
Microprocessors (8085, 8086), Linear Systems, Neural Networks, Ecommerce, Data
Structures and Object Oriented programming.
TECHNICAL
PROFICIENCIES:
Software Languages: C, C++, HTML, XML, XSL, VB.NET, ASP.NET, JavaScript
Hardware Languages: Assembly (8086), Verilog/HDL
Operating Systems: Sun-Solaris, Windows (2000/XP)
Schematic and
Layout: Cadence-Virtuoso layout
editor
Simulator: Spectre, Irsim, PSPICE, MATLAB
Office tools: MS
Office (Word, Excel, PowerPoint, Access)
Database tools:
SQL, Access
Others: LaTeX,
Adobe Photoshop
PERSONAL DETAILS:
Citizenship:
Current Visa
Status: F-1
REFERENCE:
Dr.Guoliang Fan,
Assistant Professor, glfan@okstate.edu,
(405) 744 -1547